Final-year Electronics and Communication Engineering undergraduate
Passionate final-year Electronics and Communication Engineering undergraduate with hands-on exposure to CMOS device-level design, RTL development, embedded systems, PCB design, and industry-standard EDA flows.
IIT (BHU) Varanasi
Summer 2026 (6 weeks) · Varanasi, India
Worked on the RTL-to-GDSII flow using Xschem, NGSPICE, Magic VLSI, and KLayout; learned CMOS technology and fabrication methodologies underlying the physical design flow; contributed to the design of an 8-bit ALU.
Training and Placement Cell, AKGEC
Jun 2025 – Present · Ghaziabad, Uttar Pradesh, India
Coordinated placement drive scheduling and recruiter-student communication; managed events, documentation, and on-ground operations across multiple concurrent placement drives.
Electronics Club, AKGEC
Feb 2025 – Present · Ghaziabad, Uttar Pradesh, India
Authored technical content and event scripts and anchored technical workshops and seminars for the department.
PinE Training Academy of VLSI & Embedded
10 mos · Noida
AJAY KUMAR GARG ENGINEERING COLLEGE, GHAZIABAD
10 mos
Electronics club
1 yr 5 mos
Organise and Manage events Orator
Indian Institute of Technology (Banaras Hindu University), Varanasi
2 mos · Varanasi
Bachelor of Technology, Electronics and Communication Engineering
2023 – 2027
CGPA: 7.60. Affiliated to Dr. A.P.J. Abdul Kalam Technical University (AKTU), Lucknow.
Bachelor of Technology - BTech, Electronic and Communication Engineering
Oct 2023 - Sep 2027
Designed CMOS inverter, NAND, NOR, AND, OR, and XOR layouts in Cadence Virtuoso using the gpdk90nm technology node, with 9-track, 11-track, and 13-track cell specifications. Handled transistor sizing, well/tap placement, routing, and DRC/LVS verification.
Designed and simulated CMOS inverter, logic gates, SRAM cell, and current-mirror circuits at the transistor level using Cadence Virtuoso and PSPICE. Evaluated voltage transfer characteristics, DC operating points, and current-mirroring accuracy.
Built modular Verilog RTL blocks for addition, subtraction, logic operations, and control logic; verified functionality through simulation and carried the design through synthesis-ready FPGA implementation using Xilinx Vivado.
Designed RTL modules for multiplexers, demultiplexers, buffers, a 2's-complement unit, full adder, subtractor, multiplier, and divider using Xilinx ISE, then cascaded them into a complete 8-bit arithmetic system.