B.Tech Electronics and Communication Engineering Student
Electronics and Communication Engineering student with hands-on experience in Verilog HDL, RTL design, digital logic design, CMOS VLSI, FPGA implementation, and Python-based data analysis.
8-week training and internship
Designed and simulated digital circuits using Verilog HDL; implemented and tested Verilog designs on FPGA hardware; worked with combinational and sequential digital circuits and RTL design concepts.
B.Tech, Electronics and Communication Engineering
2023 - 2027
CGPA: 8.63/10
Senior Secondary (Class XII)
2022
Percentage: 94.2
High School (Class X)
2020
Percentage: 81.2
Designed and implemented a 16-bit single-cycle RISC processor using Verilog HDL, including the ALU, registers, control logic, and datapath. Applied RTL design concepts and simulated and verified functionality using ModelSim.
Designed and implemented a digital sign calculator using Verilog HDL, synthesized and implemented it on FPGA hardware, and verified its functionality. Gained experience in RTL design, FPGA implementation, synthesis, and hardware verification.
Performed exploratory data analysis to identify customer behavior patterns and factors associated with churn. Cleaned, transformed, and analyzed customer data using Python libraries, developed an end-to-end analysis and model evaluation workflow, and deployed it as a Flask-based interactive prediction application.