Electronics and Communication Engineering Student
ECE student and aspiring RTL Design/Design Verification engineer with hands-on experience in Verilog, testbench development, functional simulation, and waveform debugging. Building digital-design projects using FSMs, counters, registers, and CMOS design tools, with a focus on VLSI internships in RTL and DV.
CENTRE FOR FUTURE STUDIES AND RESEARCH | AKGEC
1 yr 11 mos · India
B.Tech, Electronics and Communication Engineering
2023 - 2027
7.9/10, 80%
Designed and simulated a CMOS inverter using PMOS and NMOS transistors at the transistor level. Analyzed voltage transfer characteristics, propagation delay, and power consumption. Verified functionality through simulation and compared schematic-level and layout-level results using Cadence Virtuoso. Skills included CMOS design, layout design, transistor-level analysis, schematic design, and design verification.
Developed an RTL design using Verilog HDL and created a self-checking testbench for functional verification. Debugged waveform mismatches using GTKWave. Skills included Verilog HDL, FSM design, functional verification, RTL design, and ModelSim.
Developed constrained test scenarios, verified FSM transitions and timing behavior, and analyzed functional correctness through waveform debugging. Skills included Verilog HDL, FSM design, RTL design, testbench development, and ModelSim.
Designed overlapping and non-overlapping sequence detectors using an FSM architecture. Implemented RTL design and developed a verification testbench, then verified state transitions and output functionality through simulation and waveform debugging. Skills included Verilog HDL, FSM design, RTL design, and functional verification.