Manvi Jain

B.Tech Electronics and Communication Engineering student

GhaziabadElectronics, telecommunications, and semiconductor technology
3roles
23skills
1education
1credentials

About

Motivated 3rd-year Electronics & Communication Engineering student with skills in antenna design, telecommunications, embedded systems, VLSI, programming, and semiconductor research.

Experience

Research Intern

Solid State Physics Lab, DRDO

June 2026; 06 weeks

Completed a six-week research internship in the semiconductor domain, developing an understanding of microwave and RF communication systems; performed DC I-V characteristics for five systems and analyzed microwave semiconductor device behavior; researched MESFET and HEMT technologies and device architecture for 6G and terahertz communication.

Coordinator

Phoenix - Technical Society of Electronics and Communication, Ajay Kumar Garg Engineering College

March 2025 – Present · Ajay Kumar Garg Engineering College

Communicated with cross-functional teams and managed end-to-end event management for four flagship technical events, including RoboFest and Roboverse; represented the college in an inter-college bot race; led a multidisciplinary team managing events.

Member

Renaissance - Ethical, socio-cultural society, Ajay Kumar Garg Engineering College

June 2024 – Present · Ajay Kumar Garg Engineering College

Organized and managed more than five cultural events, literary competitions, and creative college fests; participated in writing, debate, and literary contests; assisted with event management, hosting, registration, and backstage coordination.

Education

Ajay Kumar Garg Engineering College

B.Tech, Electronics and Communication Engineering

Oct. 2023 – Present

Skills

VerilogSystemVerilogC++PythonMATLABNI MultisimArduino IDETensorFlowLTSpiceCSTPWMBLEWiFiHTMLCSSMS ExcelPowerPointAntenna designTelecommunicationsEmbedded systemsVLSIMicrowave and RF communication systemsSemiconductor devices

Projects

Vending Machine Controller

Designed and implemented a Verilog HDL vending machine controller using finite state machine architecture. Simulated and verified functionality with Icarus Verilog and custom testbenches; implemented coin validation, balance calculation, product dispensing, and change return logic.

Shift Register Simulation

Designed and simulated SISO, SIPO, PISO, and PIPO shift registers using Multisim. Implemented clocked flip-flop-based sequential logic circuits, validated timing constraints with a 0.5 ns margin, and optimized data synchronization and timing analysis.