Reconfigurable SRAM Controller using AXI Protocol
Designed a reconfigurable SRAM controller using Verilog HDL and AXI protocol; simulated the RTL design using Xilinx Vivado; targeted Artix-7 FPGA implementation.
Electronics and Communication Engineering Undergraduate
Electronics and Communication Engineering undergraduate with hands-on experience in VLSI Design, RTL Design, FPGA Development and Functional Verification.
InternPe
Designed and simulated CMOS Inverter, D Flip-Flop, 4:1 Multiplexer and 4-bit Ripple Carry Adder; performed schematic design, simulation and functional verification of digital circuits; gained practical exposure to CMOS logic and the VLSI design flow.
VLSI Gold Chips
Completed an intensive 5-day VLSI Bootcamp covering RTL Design, Verilog HDL and VLSI Design Flow; participated in practical digital design sessions and hands-on RTL exercises.
B.E., Electronics & Communication Engineering
2023–2027
CGPA: 8.5/10
Designed a reconfigurable SRAM controller using Verilog HDL and AXI protocol; simulated the RTL design using Xilinx Vivado; targeted Artix-7 FPGA implementation.
Implemented major modules of a RISC-V processor using RTL design techniques and performed RTL simulation to evaluate processor functionality.
Designed an FSM-based 3×1 packet router using Verilog HDL and verified the design functionality through simulation in Xilinx Vivado.
Designed and simulated a 6T SRAM cell using Cadence Virtuoso; worked with transistor-level CMOS circuit design and simulation.
Designed and simulated CMOS Inverter, D Flip-Flop, 4:1 Multiplexer and 4-bit Ripple Carry Adder; applied fundamental concepts of CMOS and digital circuit design.
Implemented FIR, IIR, FFT/DFT and other digital signal-processing experiments using MATLAB.