Award-winning ECE undergraduate specializing in RTL, Embedded Systems, and VLSI
ECE undergraduate and SIH 2025 National Winner with experience building research-grade embedded systems using C++ firmware, Python analytics, and real-time signal processing.
DRDO-SSPL
Jun–Jul 2026 · Delhi
Built two research-grade embedded systems using C++ firmware, Python analytics, and real-time signal processing.
PinE Training Academy of VLSI & Embedded
1 yr 4 mos
Understanding the foundation of VLSI domain .
AJAY KUMAR GARG ENGINEERING COLLEGE, GHAZIABAD
2 yrs 11 mos · Ghaziabad, Uttar Pradesh, India
Pursuing a B.Tech in Electronics and Communication Engineering, with a focus on VLSI design, digital electronics, and embedded systems. Engaged in hands-on projects including FPGA-based designs, circuit simulation, and hardware prototyping. Experienced with Xilinx ISE, ModelSim, and Verilog HDL for implementing and testing digital logic circuits. Building strong foundations in microcontroller programming, signal processing, and ASIC/FPGA design flow. Actively participating in technical workshops, hackathons, and industry-focused seminars to stay updated with semiconductor technology trends.
Ajay Kumar Garg Engineering College | Dr. A.P.J. Abdul Kalam Technical University (AKTU)
3 yrs 8 mos
DRDO, Ministry of Defence, Govt. of India
3 mos · India
Bachelor of Technology (B.Tech.), Electronics & Communication Engineering (ECE)
2023–Present
SIH 2025 National Winner and Team Lead. Founded two technology ventures: Krishi Netra and BharatVision.
Bachelor of Technology - BTech, Electronics and Communications Engineering
Jan 2023 - Oct 2027
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High School Diploma, Physics
Mar 2019 - Mar 2023
Was captain of the football team that was considered to be the rookies but still got 2nd position against the defending champions.
Basics to Advanced Certification Course, VLSI Design with AI
Embedded Systems with AI Certification Course, Embedded Systems with AI
Designed a Raspberry Pi 5 edge compliance system for Legal Metrology, automating manual inspections to solve a national SIH problem statement. Resulted in a patent filing, with associated research under peer review for publication. Role: Team Lead and Lead Hardware Engineer. Technologies: Raspberry Pi 5, Python, OpenCV, Edge Computing.
Engineered an ESP32-based precision agriculture rover for pesticide spraying and crop monitoring, integrating multi-sensor arrays and wireless telemetry. Role: Founder and Embedded Developer. Technologies: ESP32, Wireless Sensor Networks, Embedded C.
Designed and simulated a 4-bit signed arithmetic unit on FPGA; verified logic functionality and timing constraints via Xilinx ISE for precise 9-bit outputs. Role: FPGA Implementation. Technologies: Xilinx ISE, Verilog HDL, Digital Logic Design.
Designed, simulated, and implemented a 16-pattern Verilog LED blinker on Nexys A7 FPGA; verified logic and timing constraints in Xilinx Vivado to generate a hardware bitstream. Technologies: Verilog HDL, Xilinx Vivado, Artix-7 FPGA.
Architected a multi-module Verilog system on FPGA, integrating custom UART Tx/Rx modules for PC-to-FPGA transfer and a VGA driver for real-time video display. Role: Hardware Designer. Technologies: Verilog HDL, UART, VGA, FPGA.