I2C Master Controller
Designed an FSM-based I2C master in Verilog with START/STOP condition generation and ACK detection; verified functional correctness through simulation testbenches.
Yatharth Pathak
Final-year Electronics & Communication Engineering student
Ghāziābād, IndiaVLSI/RTL design, FPGA, embedded systems, and IoT hardware
2roles
33skills
2education
6credentials
About
Final-year Electronics and Communication Engineering student specializing in VLSI/RTL design, FPGA, embedded systems, and IoT hardware engineering.
Experience
VLSI Trainee
NIELIT
Trained in RTL design, Verilog HDL, FSM design, digital logic, and the ASIC design flow through hands-on simulation and verification exercises.
Embedded IoT Trainee
College Fab Lab
Built embedded applications on ESP32 using UART and I2C protocols for real-time sensor interfacing and data acquisition.
Education
Ajay Kumar Garg Engineering College, Ghaziabad
B.Tech, Electronics & Communication Engineering
2023 – 2027
CGPA: 7.60 / 10
Khalsa Montessori Senior Secondary School, Bulandshahr
Class XII and Class X
Class XII: 81.4%; Class X: 96.7%
Skills
Verilog HDLFSM DesignRTL DesignTestbench SimulationXilinx VivadoASIC Design Flow8051ESP32UARTI2CSensor InterfacingMQTTHTTPUDPNode-REDKiCadSchematic DesignPCB RoutingDRCLTspiceC++PythonPandasScikit-learnAI/MLVerilogPython (Programming Language)Hardware Description LanguageField-Programmable Gate Arrays (FPGA)Digital Circuit DesignVery-Large-Scale Integration (VLSI)Printed Circuit Board (PCB) DesignEngineering
Projects
Smart Fish Farm — Aquaculture IoT Monitoring System
Built an ESP32-based aquaculture monitoring system in MicroPython that tracks water quality including temperature, pH, and turbidity, publishes readings over MQTT to a Node-RED dashboard, and provides local buzzer alerts for out-of-range conditions.
Seven Segment Display Decoder
Designed a combinational Verilog decoder converting a 4-bit binary input from 0–9 to a 7-bit common-cathode display output; invalid inputs 10–15 blank all segments. Verified with Vivado behavioral simulation.
Traffic Light Controller
Developed an FSM-based traffic light controller with pedestrian-request handling and verified it through simulation across all signal states.
Smart Sensor Health Monitor
Built an end-to-end Python ML pipeline using Pandas and Scikit-learn to predict sensor health from streaming data, with visualization for anomaly tracking.
IR Sensor PCB Design
Designed the schematic and routed the PCB layout for an IR sensor module in KiCad, including full DRC verification for manufacturability.