Raj Vardhan Singh

B.Tech Electronics and Communication Engineering Student

Ghaziabad, Uttar PradeshVLSI, Digital Design, and Space Technology
1roles
24skills
1education
1credentials

About

B.Tech student in Electronics and Communication Engineering with hands-on experience in Verilog HDL, FSM-based RTL design, simulation, and digital circuit debugging. Completed a space technology internship involving rocketry systems, disaster management, and UAV applications.

Experience

Space Technology Intern

Indian Space Lab

17 June 2026 – 31 July 2026 · Remote

Worked on rocketry systems, disaster management, and advanced drone technology projects. Studied launch vehicle architecture, payload integration, satellite applications, UAV-based monitoring systems, autonomous drone navigation, remote sensing, GIS, and disaster response solutions.

Education

Ajay Kumar Garg Engineering College

B.Tech, Electronics and Communication Engineering

2023 – 2027

Relevant coursework includes Digital Electronics, Analog Circuits, Signals & Systems, Microprocessors, and VLSI Basics. Performed 15+ laboratory experiments involving digital circuit design, simulation, and debugging.

Skills

Verilog HDLCPythonModelSimVivadoProteusGitVS CodeRTL DesignFSM DesignCombinational LogicSequential LogicTiming AnalysisK-MapsDigital Logic DesignFPGA BasicsSimulationWaveform AnalysisMicroprocessorsRocketry SystemsUAV TechnologyArduino8051 MicrocontrollersPIC Microcontrollers

Projects

Space Technology Applications

Developed conceptual solutions for rocketry systems, disaster management, and advanced drone technology during the Indian Space Lab internship. Studied launch vehicle architecture, payload integration, satellite-assisted disaster response, UAV-based surveillance, autonomous navigation, and remote sensing applications. Presented findings through reports and project demonstrations.

Traffic Light Controller using FSM

Designed and implemented an FSM-based traffic light controller using Verilog HDL and ModelSim. Developed synchronous RTL with configurable state transitions and timing sequences, and verified functionality using testbenches and waveform analysis.

Binary to BCD Converter

Implemented an 8-bit Binary-to-BCD converter using the Double Dabble algorithm. Designed a 4-state FSM, verified functionality through 50+ simulation test cases, and optimized hardware utilization while maintaining accurate conversion results.