FPGA-Based JK Master–Slave Flip-Flop Implementation
Implemented an AND-gated JK master–slave flip-flop with asynchronous preset and clear based on IC 74x72. Developed behavioral and structural Verilog models, verified them using testbenches, and synthesized and tested the design on FPGA hardware with pin-compatible implementation.
Digital Arithmetic & Logic Circuits Design
Implemented half adder, full adder, ripple-carry adder, multiplexers, ALU, and shift registers. Designed behavioral and structural models with corresponding testbenches and verified functionality through simulation and waveform analysis.
Customer Segmentation System
Built a customer segmentation model using unsupervised learning techniques, including data preprocessing and clustering to derive meaningful insights.
Crack Detection System
Developed a crack detection system for image-based classification and applied preprocessing and model evaluation for surface crack identification.